555 - astable

In my previous blogs, we saw how 555 can be configured as a bistable (latch) or monostable (single pulse) signal generator. In this blog I would be delving into the astable configuration for 555.

So, what is the astable mode? In the context of 555, astable mode is that mode of operation when the output pin (Pin 3) perpetually oscillates predictably between HIGH and LOW voltages without external interventions. I have highlighted some parts of the definition which needs special mention.

• Predictability is referred to in terms of the value of HIGH and LOW and the time that the output stays in those states.
• External input implies any input to the astable circuitry apart from a DC power source.

Note that a term 'duty cycle' is used frequently in the context of astable outputs. Duty cycle is quite simple - it is equal to the %age of time the signal stays HIGH in one time period. So for example, if we have a time period of 4 seconds and the signal is HIGH for 1 sec (remaining 3 seconds, it's LOW), the duty cycle of the signal is 25%. capeesh?

Now, let's get into the interesting part - how do we go through the process of building one using 555.

Let's pick up from where we left the monostable circuit.

There we needed a negative (<1/3 Vcc) pulse at the trigger (Pin 2) to set the output high. As soon as the pulse starts, the discharge pin stops grounding and the capacitor starts charging. After a certain time (determined by the value of R and C) the capacitor reaches a voltage > 2/3 Vcc. When this happens the output is set to low and pin 7 gets grounded, causing the capacitor to discharge.

To extend the monostable circuit for astable operation, we need the an automated mechanism to trigger Pin 2 and 6, repeatedly at configurable time intervals.

So, how do we do that? We rewire the circuitry as follows:

The part that is of interest to us is the path from Vcc through R1, R2, C and ground. Also note how the 555 pins are connected, 7 is connected between R1 and R2, 6 and 2 are fused and the cap C1 is connected between 2 and ground.

Lets walk through the step sequence for two operation cycles and see how the circuit works. Let's start at an initial state when the circuit is just powered up, ergo, the output (pin 3) is low and C1 is discharged at the start moment.. but not for long...

1. Since C1 is discharged, pin 2 is grounded. This meets the criteria of having a low (<1/3 Vcc) at pin 2 and hence the output goes high. 
2. Once the output goes high, the threshold pin become ungrounded, implying that current now flows through Vcc, R1, R2 and starts charging C1.
3. The charge on the cap is reflected on pin 6 and 2. Output is still high and the charge on C1 is steadily rising.
4. The charge on cap touches 2/3 Vcc and rises... wham, the threshold (Pin 6) is triggered and output goes low, causing 7 to get grounded.
5. Once 7 is grounded there are two separate current flows. First one is from Vcc through R1 and grounded through 7. Second one is the discharge current from the capacitor.
6. Capacitor starts discharging from 2/3 Vcc and starts sliding down. 
7. Soon it tips just below 1/3 Vcc and wham.. pin 2 is triggered. Causing the output to go high. So we are back to step 2 and the cycle continues.

Let's overlay the above on a voltage time graph and a real life oscilloscope. Hope this drives the concept home.. next we will delve into a bit of mathematics to understand and control the precise nature of the output waveform.

The mathematics behind

Few important considerations to keep in perspective before we go forward:

1. The output is high while the capacitor is charging and low when the capacitor is discharging
2. The capacitor charges and discharges only between 2/3 Vcc and 1/3 Vcc

As a recap, for a RC circuit the charging and discharging equations are:

Here R' is the resistor through which the capacitor is charging towards Vcc and t2-t1 is the time that the capacitor takes to charge from 1/3 Vcc to 2/3 Vcc. Now the discharging part...

Here R" is the resistor through which the capacitor is discharging. Now see the image below which shows the path of current flow during the charge and discharge cycles. It can be seen that the capacitor charges through both the resistors (R1+R2) but discharges only through (R2).

Therefore, substituting R1+R2 for R' and R2 for R" in the above equations we realize that the On and Off times are

Taking it a bit further, the time period is t_on + t_off

and hence the duty cycle is t_on / T, i.e

Limitations

There is something of interest hidden in the formulas above.. do you see that the on time is always greater than the off time, due to R1? This implies that the duty cycle obtained from this configuration can never be less than 50%. This might be a serious limitation in cases where we are interested in pulse type of waveforms which have a very small duty cycles.

To remedy the situation, the circuitry can be wired a bit differently as shown below:



See the parts marked in red. All it does it channelize the charge and discharge currents so as to overcome the limitation of >50% duty cycle. See how the change current is constrained to flow thrugh R1, D2, left part of R2; while the discharge current is routed through right part of R2, R3 and D1. I have take a PWM circuit to explain the concept, and hence the R2 pot. You can just place two resistors in series of the diode to make life simple.

Second big limitation is accuracy. 555 progressively looses accuracy for larger time periods (exceeding a few minutes). This is of the large capacitor tolerances. If you are looking at 555 for very low frequency (0.0x Hz) scenarios, it is better to use IC4060, which is a 14 stage binary ripple counter and can give you time periods in hours and days.

Third limitation is fast switching. If you are operating on the other end of spectrum (tens to hundreds of KHz), a slight load on the output will seriously influence the leading edge taper. See the scope snapshot below.

If you need a sharp leading edge irrespective of driving load (at high frequencies), you are better off driving a high impedance op-amp buffer or a switching mosfet at the output.

Lastly another important thing worth mentioning is the difference between TTL and CMOS 555 varieties. CMOS versions (TLC555 or ICM7555 chips) are costlier but give a much better output as compared to TTL 555. CMOS 555 chips can give close to rail voltages at the output and show much less distortion and ringing even when operating under moderate load.