IC 555 - Demystified (inside out)

So why another manuscript for an iconic integrated circuit which was introduced in 1972 and claimed to be the most popular integrated circuit ever manufactured?

Quite simply put, I struggled to find a literature which demystifies 555 from bottoms up, without stressing out the reader with the full schematic (or block diagram) as the starting point. A bottoms up view makes us realize the full potential to which this iconic and legendary IC can be exploited.

Contrary to the popularly held belief, 555 is NOT a timer! In fact, the chip in itself has no comprehension of time - it is the peripheral circuitry which feeds in the notion of time into the chip. Secondly, again contrary to the popular beliefs it is also not inherently a pulse generator - the chip in itself has no intelligence of when to start or end a pulse. So then, what is the inherent nature of 555?

555 from my perspective is nothing but a glorified SR flip-flop! The 'glory' part surrounding the flip-flop is the functionality of setting the voltage thresholds to drive the SR inputs and a feedback from the SR output Q to provide a current sink when the output of the IC is low. The latter is a nifty addition to facilitate building the peripheral circuitry - more of it in a moment! For now, feel free to forget the text highlighted in blue if that has confused you.

Let's start by taking a basic SR flip flop and constructing the 555 schematic around it, pausing often to understand and appreciate the rationale of extension.

SR flip-flop is a simple 1 bit memory storage circuit. It can also be thought of as a 1 bit latch. The state of the latch is accessible through its output (Q) and controlled by the inputs Set (S) and Reset (R). SR flip-flop also has another output Q' (Q Bar or Q Complement) which gives an inverted state of Q - so if Q is 0 then Q' will be 1 and vice versa. Below is a diagram which lays down the symbol, timing sequence diagram and the truth table. As you can see, its quite simple.

As I have mentioned earlier, it is around this SR flip flop that the 555 design builds upon. As a first addition, 555 design introduces voltage controlled set and reset trigger for the flip flop. What that means in lay man terms is that now we can decide the level of voltages at which the set and reset pin of the SR flip flop is triggered. How is this useful? This gives us analog control over the flip flop - for example, now we can make the SR flip flop set the latch only if the S input is greater than some defined voltage. Quite a few possibilities emerges just out of this set up. Below is a diagram which explains the layout.

The port numbering (6, 2, 3) is quite intentional. They match with the IC pinout! With this set up, the truth table of the flip flop becomes as follows. The interesting thing to note is the criteria of triggering S or R. The Set pin is trigger when the threshold voltage exceeds V1, while the Reset pin is triggered when the trigger voltage dips below V2.

Now comes the second addition to 555 design - the voltage dividers. The IC has three 5K resistors in series connected between Vcc (pin 8) and GND (pin 1). [ Vcc - R1 - R2 - R3 - GND ]. This implies that the voltage at the junction of R1 and R2 is 2*Vcc/3, while the voltage at the junction of R2 and R3 is Vcc/3. It is these junction voltages that are connected to the negative and positive inputs of comparators 1 and 2 respectively. Note that these reference voltages remain steady as the input impedance of the comparators are close to infinite.

So, what's the rationale and consequence? The rationale and consequence is that the chip gives us a preset and well stabilised voltage levels against which we can operate the set and reset pins without the need of external circuitry. Did you know that the name of the IC comes from the choice of using three 5K resistors in this configuration (5-5-5)! Does this constrain us? not really. The chip has inbuilt provision which gives us the ability to change the reference voltage levels. See the diagram below.

As you can see, the Pin 5 of the IC (Control pin) is directly connected to the negative pin of the threshold comparator. This means, we can apply a voltage to this pin to control the comparator thresholds (yes, that's right - both the comparator thresholds). The important thing to note is that there is no separate threshold control provision provided for the trigger comparator (CMP2). Also, we have to be cognizant of the fact that if we are providing external voltage to override the default comparator reference voltages, it will also influence the trigger comparator threshold - i.e. it will no longer be Vcc/3 but will be the half of the control voltage. The ability to define the reference voltages of the comparators opens up great exploitation opportunities! I will show you some use cases which can be realized by using the ability to change the comparator reference voltages later on. In most cases (typical usage), we really don't bother tweaking the preset references and hence don't really need pin 5. We park it in a harmless state by tying it to ground via a 0.01uF or lesser capacitor.

We have pretty much covered 6 out of the 8 pins of the IC. Let me talk a bit about the Pin 4 (Reset) before I move to the last one Pin 7. The reset pin (Pin 4) is quite simple - it connects to the master reset of the flip-flop via an inverting gate. This means that the reset pin of the IC is an active low pin - that is, it triggers the reset functionality on a negative edge pulse (when the voltage dips below 0.7V). Important thing to remember is that an active low signal to this pin force resets the state of the output (Pin 3) to 0, irrespective of the state of the threshold (Pin 6) and control (Pin 2) inputs. This has its uses. For example - an active low trigger on this pin can be used to prematurely terminate a high output on pin 3, acting much like an abort trigger. The terminated output will not be set to high till the next output set trigger. However, in most of the cases, we tie this pin along with Vcc (Pin 8) so that it doesn't interfere with our working. The diagram below shows how Pin 4 is connected.

Now to the final pin, Pin 7 - the discharge pin. The diagram below shows how the discharge pin is engineered. It is connected to the collector of an NPN transitor, whose base is controlled by the Q output of the flip-flop and the emitter connected to ground.

Remember that Q and Q' are complementary and hence the transistor goes into a saturation state (effectively shorting the voltage on Pin 7) when the output (Pin 3) is low. Put another way, when the output (Pin 3) is high, the voltage on the discharge pin is not influenced. However, the moment the output (Pin 3) goes low, the voltage on Pin 7 is grounded instantaneously. On the surface, the piece of functionality seems completely disjoint and feels like an unexplained extension - however, this pin plays a key role in assisting the peripheral circuitry to leverage this functionality to drain the charge building on a capacitor connected to this pin. In short, this pin is the key which enables the 555 chip to sense time! In later parts of this blog series, I will show with examples how the peripheral circuitry is built.

To summarize - the diagram below shows all the pins of the 555 chip. Look out for the next few installments of this blog series to see how we can use 555 IC to build different types of circuits based on the concepts presented here.