555 - Monostable

Welcome to the fourth blog in the '555 - Demystification' series! In this blog, I will attempt to demystify the monostable operation mode of 555. Why another blog on the subject - you might ask? Well, simply put, I couldn't find any on the subject which could paint a comprehensible picture for my early teen son :)

Back to the topic, then! The problem we are trying to address is as follows - We want to design a circuit using the 555 IC, which once triggered will maintain the high output state (Pin 3) for a pre-defined period of time, before resetting the output pin to low. The diagram below explain the ask pictorially.

So, what's the big deal about it? Well, we built the bi-stable circuit using 555 earlier, but that had a CLR button to bring down (reset) the output state. In this case, the reset is accomplished automatically and precisely after a pre-defined period of time. What makes it interesting is that we will be introducing the intelligence of  'sensing' elapsed time in the circuitry.

Incidentally, this type of behaviour is also called 'Monostable', since it has one stable state (0) and tends to return to the stable state after any trigger - though after a period of time.

Before we start assembling the magical circuitry, let's spend a few moments on the concept of 'sensing' elapsed time in the electronic world. Note that I have been using the word 'elapsed time' instead of just time. Just time is absolute, but elapsed time is relative to a marker - in our case the moment we triggered the output to high.

There are many ways of measuring time - rely on a clock, count pulses etc. However, there is another simple and cheap mechanism which is very common when it comes to time measurement. The charging of a capacitor ! A capacitor charges and discharges very predictably when a voltage is applied across it through a resistor. If you want to know more about how a capacitor charges and discharges read this first. In short, the charge build up across a capacitor in an RC circuit is in accordance with the below (mathematically defined and hence precise) curve.

In the above equation, V is the voltage across the capacitor, Vcc is the source (max) voltage, R & C are the values of Resistor and Capacitor respectively and t is the time required for a voltage V to build up across the capacitor.

Great! So, we can precisely predict what will be the voltage across the capacitor after time t, or conversely how much time will it take for a certain voltage to build up across the capacitor. The practical question is - how do we build a circuit to act on the time or voltage trigger? See the circuit below:

With the above circuit, we have accomplished the following:

1. Set up a mechanism to establish a precise voltage (or time) reference using a voltage divider (R1 and R2). If, R1 = R2 then the voltage reference is 1/2 Vcc etc.
2. Used a voltage comparator to output a high when the capacitor charge exceeds the voltage reference.

In essence, the output of the comparator will go to high after the time required to charge the capacitor to the voltage reference set by the divider.

Let's continue building on it further. Now let's build more circuitry to automatically reset the timer after triggering an output. See the circuit below:

The above circuit consists of the following parts:

1. Green components (R1 & R2) - Voltage divider used to set reference point
2. Blue components (R & C) - RC circuit used to measure time
3. The comparator (OP1)
4. Orange components (R3 and T1) - Reset machinery

So how do they work in unison? 

• OP1 output remains low as long as the capacitor is charging. This causes the transistor T1 to remain off - implying that the voltage at the transitor collector and the comparator +ve pin continues to reflect the voltage across the capacitor. 
• After some time the voltage across the capacitor reaches a value above the one set by the resistors (R1 and R2) and the OP1 output goes high. 
• As soon as OP1 output goes high, it switches on the transistor effectively grounding the collector thus resetting the timing device.

There is one important point to note though. The moment the capacitor is grounded by the transistor, the output of the comparator goes back to 0. This implies that the high output of OP1 is momentary and we will need some more circuitry to make good use of it. But the circuit above is quite helpful in demonstrating the concepts of setting time thresholds, tracking time, triggering on threshold breach and then resetting the timer.

If you are with me so far, the rest of the journey is going to be downhill from here :)

Before I show you how to build the circuit with 555, I will take a moment more to refresh your memory of 555 internals with special attention to Pin 7, the Discharge pin. The above diagram shows how it is positioned. It is worthwhile to remember that when the Output is LOW, the Discharge pin is grounded and consequently when the Output is HIGH, the Discharge pin is not connected to ground.

Easy way to remember - Output Pin LOW - Discharge Pin LOW

The circuit below unveils the 555 monostable operation circuit (finally!) based on the understanding we have built above. Let's start with the interpretation of the timing sequence diagrams to the right. It contains four time markers:

• t0 - The instant of powering up the circuit
• t1 - The instant when the SET switch is pushed
• t2 - The instant when the SET switch is released
• t3 - The time when the output pulse resets itself

It is assumed that the time taken to push the switch is quite less as compared to the pulse width. Don't get hung up on this assumption - we will dissect it later, for now just accept it :)

Let's analyse the behaviour of the circuit in reference to the time markers t0-3.

When the circuit is switched on, Pin 2 (trigger) is pulled to high via R1 and Pin 6 (Threshold), Pin 7 (Discharge) are effectively grounded (because C1 is not charged up yet). This forces the output to LOW. Remember Pin 7 is grounded when the output is low effectively preventing the capacitor from charging through R. This state continues till time t1.

At t1, the SET button is pushed and released quickly, effectively sending a negative pulse to the trigger pin (Pin 2). This causes the output to go high and Pin 7 to decouple from ground. From this point onwards, the capacitor C starts charging through R5 and voltage at Pin 6 starts to build exponentially. Remember that Pin 6 is connected to the first comparator (CMP1) within the 555 IC. The reference voltage for CMP1 is maintained at 2/3 Vcc through the three 5k resistor chain. The capacitor charging will continue till it reaches 2/3 Vcc. The equations below show that it will take 1.1 * R5 * C1 seconds for the capacitor to reach a voltage equal to 2.3 Vcc.

As soon as the voltage across the capacitor reaches 2.3 Vcc, CMP1 triggers a high - effectively resetting the output. Hence 1.1 * R5 * C2 defines the width of the monostable pulse.

Now as soon as the output is reset, Pin 7 gets grounded, immediately pulling the capacitor voltage to 0 - resetting the whole mechanism. The monostable circuitry will remain in this state till it is triggered by switching in on via the push button switch.

I hope this explanation helps appreciate (and not just understand) how a monostable circuit using 555 is constructed and works!

555 - Power on state

Previous blogs in this series:

1. 555 Demystified
2. 555 as a latch

In the last blog, I wrote about how to use the 555 as an one bit latch - the simplest of use cases. Incidentally the resulting circuit is also called bi-stable mode of 555. In this blog, we will build further on it. For ease of reference here is the circuit we built last time.

In the first blog, we learnt that Pin 3 will go high if SET (Pin 2) is pulled low (SET button is pressed) and CLR (Pin 6) is low (CLR button is not pushed). But, what about the t=0 condition in the circuit above? t=0 condition is the initial state of Pin 3, the moment power is turned on.

In the above circuit, assuming both the buttons are open (not pushed) - Pin 6 will be pulled down via R2 and Pin 2 will be pulled up via R1. Now let's refer to the diagram below which shows how the inputs at Pin 6 and 2 influence the output.

With Pin 6 at 0 - CMP1 will output 0 (low), while with Pin 2 at 1 (high) - CMP2 will output 0. So that initial input into the SR flip-flop is 0-0 for S-R respectively. This implies that the output will remain unchanged. Since right before power up, the output was low it will start with a low state when the power is turned on.

All good so far! So, can we be assured that the output will be always low on power-up. :) Unfortunately, not. Relying on the above logic to get a deterministic low output on startup is not a great idea. The most common cause is stray capacitance in the circuitry which feeds to the trigger pin or the stray capacitance of any switches connected to pin 2.

Secondly, what about the case where we want the output to be high on power-up?

The above use cases are called power-up set/reset use cases and we need extra circuitry to cater for them in a deterministic way.

Low output state at startup

There are multiple strategies to force a low output state at startup. The two most common ones are to

• Solution A ) Force the reset pin (Pin 4) to be low at startup, transitioning to high in some finite but small period of time.
• Solution B ) Force the threshold pin (Pin 6) to be high at startup, transitioning to low in some finite but small period of time.

Below are two common strategies to force Pin 4 to a grounded state at power up. In the first strategy, the collector of T1 is grounded as C1 is charging up through R2. In the second strategy, (which works just as good), C2 is effectively shorted at startup and slowly builds up voltage as it charges through R3 - effectively pulling Pin 4 to ground.

Shown below is a simple strategy to pull Pin 6 to high at power up. At the start C2 is effectively shorted, forcing Pin 6 to be high. As time passes, C2 charges up and in the process Pin 6 is pulled down to ground in due course. As Pin 6 starts up high, the output is effectively 0 on power up.

High output state at startup

There are cases where you might want 555 to start up on a high output state at power up. For example, I have a garden irrigation system which operates via a monostable pulse of 555. In this case, I want the 555 to operate my solenoid valve as soon as I power up the circuit and subsequently on a trigger. To achieve this, we simply build on the strategies discussed above - in this case, we keep Pin 2 and 6 pulled down at startup.

I have intentionally left other pins in the diagrams as the strategies discussed above are independent of the configuration of other pins.

Stay tuned for the next instalment in this series, where I will start discussing about the monostable and astable operation modes of the 555 chip.

Simplest of 555 circuits - one bit latch

Earlier instalments in this series:

1. IC 555 Demystified (inside out)

Before we delve into appreciating the full potential of 555, let's start off with the simplest of circuits - A single bit latch. You might be interested in glancing through my previous blog on 555 Demystified to get some bearing on this blog.

Let's start by taking care of the simple pins first. Note that the circuits shown below are intermediate circuits and will not work as is - they are just step by step explanations of how to build the final circuit.

1. Pin 1 - Grounded 
2. Pin 8 - Connected to Vcc
3. Pin 4 - Connected to Vcc - Remember this is the active low reset pin which we tie to Vcc to ensure that it accidentally doesn't cause any resets. More of a safeguard.
4. Pin 5 - Control pin. We don't need to play with the upper comparator threshold and hence we park this pin by connecting it to ground via a 10nF capacitor
5. Pin 7 - Discharge pin. We don't need to leverage the discharge feature and hence we park this pin by connecting it to ground via a 10nF capacitor.

Life become much simpler when we have taken care of 5 out of 8 pins :) Let's tackle the remaining three, starting with Pin 3 - the output pin. See the diaram below.

I have connected two LEDs (1 and 2) to Pin 3 in such a way that LED1 will glow if Pin 3 acts as a sink (GND) and LED2 will glow if Pin 3 acts as a voltage source. An interesting observation - the output pin can work both as a source and sink! able to source and sink as much as 200 mA of current (quite a bit of current for small to medium scale driver requirements). The above arrangement ensures that LED2 glows when Pin 3 is HIGH (sourcing current) and LED1 glows when Pin 3 is LOW (sinking current).

Now, let's continue building our circuit around Pin 6. Remember that Pin 6 is the threshold pin and it sets the internal SR flip flop if the voltage at Pin 6 exceeds 2*Vcc/3. Since the output of 555 (Pin 3) is derived from the complemented output of the flip-flip, a positive pulse on Pin 6 effectively sets the output at Pin 3 to LOW.

In the circuit above, I have connected Vcc to Pin 6 via a push switch (CLR) and a pull down resistor (R2). Why the pull down resistor? To ensure that when the switch (CLR) is not connected, the voltage at Pin 6 is pulled down to GND via R2.

Let's tackle the last pin (Pin 2). Remember that Pin 2 is the trigger pin (Active Low) - implying that if a negative pulse ( < Vcc/3 ) is applied to this pin, it sets the output (Pin 3 to high) and Pin 3 will continue to remain at high till it is reset either via the Pin 6 or Pin 4. (In our case Pin 6).

In the circuit above, I have connected ground to Pin 2, via push button (SET) and a pull up resistor R1. Why a pull up resistor? - to ensure that Pin 2 receives a HIGH till we activate it via the SET button. Remember again, that a negative pulse is required to activate Pin 2. Pushing the SET button instantaneously grounds the Pin 2, providing a negative pulse.

And so, we have our final circuit. Let's see how it behaves. As the first use case, let's push the SET button (diagram below).

As expected, pushing the SET button, ground the Pin 2, sending a negative pulse and consequently setting the output pin 3. This will in-turn cause the LED2 to glow. Note that LED2 will continue glowing, i.e. Pin 3 will continue to be in a HIGH state even after the SET button is released. Effectively, we have latched an output state by a (negative) trigger pulse at Pin 2.

As the second use case, let's push the CLR button (diagram below).

Again, as expected, pushing the CLR button, provides a HIGH pulse to pin 6, effectively resetting the output state to LOW, in turn causing Pin 3 to sink which in turn causes LED1 to glow. Note that LED2 will switch off when LED1 is glowing. LED1 will continue to glow, i.e. the output Pin 3 will continue in its LOW state till we provide a SET pulse again.

If you have followed it till here, you have pretty much understood 90% of the magic we can accomplish with 555. It all boils down to how we control the inputs at Pin 6 and 2 (optionally by leveraging Pin 7).

The remaining 10% is about playing with Pin 5 to dynamically control the reference voltages of Pin 6 and 2, but we will leave it for now and cover it later in the series. Stay tuned for the next instalment where I will talk about achieving a deterministic state of the output at the instant of powering up the circuit - Power up set/reset.

IC 555 - Demystified (inside out)

So why another manuscript for an iconic integrated circuit which was introduced in 1972 and claimed to be the most popular integrated circuit ever manufactured?

Quite simply put, I struggled to find a literature which demystifies 555 from bottoms up, without stressing out the reader with the full schematic (or block diagram) as the starting point. A bottoms up view makes us realize the full potential to which this iconic and legendary IC can be exploited.

Contrary to the popularly held belief, 555 is NOT a timer! In fact, the chip in itself has no comprehension of time - it is the peripheral circuitry which feeds in the notion of time into the chip. Secondly, again contrary to the popular beliefs it is also not inherently a pulse generator - the chip in itself has no intelligence of when to start or end a pulse. So then, what is the inherent nature of 555?

555 from my perspective is nothing but a glorified SR flip-flop! The 'glory' part surrounding the flip-flop is the functionality of setting the voltage thresholds to drive the SR inputs and a feedback from the SR output Q to provide a current sink when the output of the IC is low. The latter is a nifty addition to facilitate building the peripheral circuitry - more of it in a moment! For now, feel free to forget the text highlighted in blue if that has confused you.

Let's start by taking a basic SR flip flop and constructing the 555 schematic around it, pausing often to understand and appreciate the rationale of extension.

SR flip-flop is a simple 1 bit memory storage circuit. It can also be thought of as a 1 bit latch. The state of the latch is accessible through its output (Q) and controlled by the inputs Set (S) and Reset (R). SR flip-flop also has another output Q' (Q Bar or Q Complement) which gives an inverted state of Q - so if Q is 0 then Q' will be 1 and vice versa. Below is a diagram which lays down the symbol, timing sequence diagram and the truth table. As you can see, its quite simple.

As I have mentioned earlier, it is around this SR flip flop that the 555 design builds upon. As a first addition, 555 design introduces voltage controlled set and reset trigger for the flip flop. What that means in lay man terms is that now we can decide the level of voltages at which the set and reset pin of the SR flip flop is triggered. How is this useful? This gives us analog control over the flip flop - for example, now we can make the SR flip flop set the latch only if the S input is greater than some defined voltage. Quite a few possibilities emerges just out of this set up. Below is a diagram which explains the layout.

The port numbering (6, 2, 3) is quite intentional. They match with the IC pinout! With this set up, the truth table of the flip flop becomes as follows. The interesting thing to note is the criteria of triggering S or R. The Set pin is trigger when the threshold voltage exceeds V1, while the Reset pin is triggered when the trigger voltage dips below V2.

Now comes the second addition to 555 design - the voltage dividers. The IC has three 5K resistors in series connected between Vcc (pin 8) and GND (pin 1). [ Vcc - R1 - R2 - R3 - GND ]. This implies that the voltage at the junction of R1 and R2 is 2*Vcc/3, while the voltage at the junction of R2 and R3 is Vcc/3. It is these junction voltages that are connected to the negative and positive inputs of comparators 1 and 2 respectively. Note that these reference voltages remain steady as the input impedance of the comparators are close to infinite.

So, what's the rationale and consequence? The rationale and consequence is that the chip gives us a preset and well stabilised voltage levels against which we can operate the set and reset pins without the need of external circuitry. Did you know that the name of the IC comes from the choice of using three 5K resistors in this configuration (5-5-5)! Does this constrain us? not really. The chip has inbuilt provision which gives us the ability to change the reference voltage levels. See the diagram below.

As you can see, the Pin 5 of the IC (Control pin) is directly connected to the negative pin of the threshold comparator. This means, we can apply a voltage to this pin to control the comparator thresholds (yes, that's right - both the comparator thresholds). The important thing to note is that there is no separate threshold control provision provided for the trigger comparator (CMP2). Also, we have to be cognizant of the fact that if we are providing external voltage to override the default comparator reference voltages, it will also influence the trigger comparator threshold - i.e. it will no longer be Vcc/3 but will be the half of the control voltage. The ability to define the reference voltages of the comparators opens up great exploitation opportunities! I will show you some use cases which can be realized by using the ability to change the comparator reference voltages later on. In most cases (typical usage), we really don't bother tweaking the preset references and hence don't really need pin 5. We park it in a harmless state by tying it to ground via a 0.01uF or lesser capacitor.

We have pretty much covered 6 out of the 8 pins of the IC. Let me talk a bit about the Pin 4 (Reset) before I move to the last one Pin 7. The reset pin (Pin 4) is quite simple - it connects to the master reset of the flip-flop via an inverting gate. This means that the reset pin of the IC is an active low pin - that is, it triggers the reset functionality on a negative edge pulse (when the voltage dips below 0.7V). Important thing to remember is that an active low signal to this pin force resets the state of the output (Pin 3) to 0, irrespective of the state of the threshold (Pin 6) and control (Pin 2) inputs. This has its uses. For example - an active low trigger on this pin can be used to prematurely terminate a high output on pin 3, acting much like an abort trigger. The terminated output will not be set to high till the next output set trigger. However, in most of the cases, we tie this pin along with Vcc (Pin 8) so that it doesn't interfere with our working. The diagram below shows how Pin 4 is connected.

Now to the final pin, Pin 7 - the discharge pin. The diagram below shows how the discharge pin is engineered. It is connected to the collector of an NPN transitor, whose base is controlled by the Q output of the flip-flop and the emitter connected to ground.

Remember that Q and Q' are complementary and hence the transistor goes into a saturation state (effectively shorting the voltage on Pin 7) when the output (Pin 3) is low. Put another way, when the output (Pin 3) is high, the voltage on the discharge pin is not influenced. However, the moment the output (Pin 3) goes low, the voltage on Pin 7 is grounded instantaneously. On the surface, the piece of functionality seems completely disjoint and feels like an unexplained extension - however, this pin plays a key role in assisting the peripheral circuitry to leverage this functionality to drain the charge building on a capacitor connected to this pin. In short, this pin is the key which enables the 555 chip to sense time! In later parts of this blog series, I will show with examples how the peripheral circuitry is built.

To summarize - the diagram below shows all the pins of the 555 chip. Look out for the next few installments of this blog series to see how we can use 555 IC to build different types of circuits based on the concepts presented here.